00000000000000000000000000000000000000000000000000000000000000000000008101725161117131414861071113141288141012813202420182422221918200000000000000000000000000000000000000000000000000000000000000000000000We proposed a fault diagnosis method for a single universal logical fault model using multi-capture cycle test sets for full scan design circuits and evaluated the diagnosis performance. Our proposed method was able to correctly diagnose fault locations for faulty circuits with open faults or dominant bridging faults. The method was able to narrow down the number of suspicious candidate faults to less than 1.5％ of all faults in circuits on average.Our future work includes ranking suspicious candidate faults, applying our proposed method to faulty circuits with delay faults and reducing the number of suspicious candidate faults by applying don’t care (X) identification and X-filling techniques for fault diagnosis to test sequences.This work was supported in part by Japan Society for the Promotion of Science (JSPS) under Grants-in-Aid for Science Research C (No.26330071).Table 4 Experimental Results of Diagnosis Performance and Diagnosis TimeBridging faultsCircuitskProposedPreNonMisPreNonMisPreNonMisPreNonMis1211100000101020000054220102010000011002100310041005100110021003100410051001100210031004100510011002100310041005100110021003100410051001100210031004100510011002100310041005100S5378S9234S13207S35932S38584b14b15Diagnosis performanceSAF110001000100110001000100210021002100010011001100010001001100010001002100210001002100110001000100010011000100010011001100010001000100010001009190837484898185848691939093888786869092848988928779768081757878818280Open faultsProposedSAF1112161420141313181528332825323330293026342227172416211716131014128128886838579868787828571677175666770717074617471817683798184869086889288─ 16 ─Diagnosis timeBridging faultsSAFProposed0.30.40.91.21.10.61.32.83.43.71.62.74.25.510.51.11.72.03.94.26.315.222.742.853.20.81.71.93.04.00.82.43.77.114.20.30.81.83.03.11.45.28.512.117.16.35.216.210.112.20.91.21.32.22.411.433.475.1121.1144.97.316.017.327.436.37.623.836.168.7130.9Open faultsProposed0.20.40.81.01.11.22.33.75.85.71.32.34.75.410.61.52.12.93.95.710.110.816.833.451.80.82.74.36.28.60.50.81.42.65.0SAF0.40.81.53.13.61.54.16.510.818.88.815.624.036.156.01.01.72.53.55.532.857.2174.1139.6457.97.926.241.760.884.65.27.313.525.649.75. ConclusionAcknowledgements
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