and ft2. When ft1 is applied to CUT, the error behavior 4 and 6 of the faulty line n and the error behavior 5 and 6 of the faulty line m are explainable for the test responses. When ft2 is applied to CUT, the error behavior 4 of the faulty line n is explainable for the test responses, but all the error behaviors of the faulty line m are not explainable for the test responses. Thus, n is deduced as a suspicious candidate fault.Fault simulation for universal logical faults is time-consumed. Thus, after candidate faults are generated by applying an erroneous path tracing method16), fault simulation for the candidate faults is performed.In this paper, a fault diagnosis method for stuck-at faults such as5) and our proposed method were applied to faulty circuits with dominant bridging faults or open faults, and the diagnosis results were compared. Dominant bridging faults are merely called as bridging faults from now on. In this paper, the two diagnosis methods were applied to five ISCAS’89 benchmark circuits and two ITC’99 benchmark circuits. 100 faulty circuits with bridging faults and 100 faulty circuits with open faults for each benchmark circuit were made. The number of suspicious candidate faults, diagnosis performance, and diagnosis time were evaluated.Table 3 shows the numbers of suspicious candidate faults and fanout-free regions (FFRs) for faulty circuits. In Table 3, “Circuits” denotes the name of circuits, “k” denotes the number of capture cycles at testing, “Suspicious candidate faults” denotes the number of suspicious candidate faults, “Suspicious candidate FFRs” denotes the number of FFRs with one or more suspicious candidate faults, “Bridging faults” denotes the experimental results of fault diagnosis methods for faulty circuits with bridging faults, “Open faults” denotes the experimental results of fault diagnosis methods for faulty circuits with open faults, “Proposed” shows the experimental results of our proposed fault diagnosis method, and “SAF” shows the experimental results of the fault diagnosis using stuck-at fault simulation. “Ave”, “Max”, “Min”, and “Mode” denote the average, the maximum value, the minimum value, and the value with the highest frequency, respectively.In the proposed method, the numbers of suspicious candidate faults were 3.3 to 32.9 on average, and the mode values were 1 to 13. In many cases, the mode values were 2 to 5. The numbers of suspicious candidate FFRs were 1.1 to 7.7 on average, and the mode values were 1 to 8. The mode values were 1 for all circuits except for s9234. It found that suspicious candidate faults concentrated in an FFR. Since fault activation conditions are not cleared in the universal logical fault model, all the signal lines on the path from the faulty line to the output of FFRs are deduced as suspicious candidate faults. Therefore, when the number of signal lines from a faulty line to the output signal line of an FFR is large, the number of suspicious candidate faults becomes large. As shown in Table 3, the average number of suspicious candidate faults varies greatly depending on circuits, but it can be seen that the average number of suspicious candidate FFRs is 5 or less in most circuits. Our method deduces not types of faults but faulty lines. Postprocessing is required to deduce types of diagnosed universal logical faults.In the method using stuck-at fault simulation, only when fault locations were correctly deduced, the number of suspicious candidate faults was shown in Table 3. It seemed as if the fault diagnosis method using stuck-at fault simulation Table 2 Example of Fault Diagnosis for Universal Logical Faults (k＝3)error behavior3.4.2 Fault Diagnosis for a Single Universal Fault Model4.1 The Number of Suspicious Candidate Faultstime231PFerror behavior 1Perror behavior 2PFPerror behavior 3PFFerror behavior 4FPPerror behavior 5FPFerror behavior 6FFPerror behavior 7FFFft101111000110011ft201100111010011ft111011001000011─ 14 ─observed valuesnmft1ft21010010001001000ft2114. Experimental Results
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