3FPFPFPF2PFFPPFF■■■■■■and stuck-at 0 fault on g, respectively. The pass test sequence detects a/0 and b/0, and does not detect g/0. Therefore, the final suspicious candidate fault becomes {g/0} by F-{a/0, b/0}. a/0 and b/0 are not explainable faults though there exists the bridging defect between a and b. While, g/0 is an explainable fault. This diagnosis is misprediction17). In this paper, we propose a universal logical fault model to prevent misprediction17) and non-prediction17).In this paper, we do not classify a logical fault model which changes logical function of a circuit and define a logical fault to a signal line. When the number of cycles at each capture mode is k (k＞1), a time expansion model of CUT is treated as a circuit with a multiple fault model. In fault diagnosis for multi-cycle capture testing, a universal logical fault model is expressed in whether a fault on a signal line is activated or not at each time frame. In other words, the model is treated based on activated time frames.Fig.4 is an example of a universal logical fault on the line n in 3 time expansion model of 3-cycle capture testing. Table 1 shows the behaviors of the universal logical fault on the line n in Fig. 4. In Table 1, F expresses that the fault on the line n is activated, while P expresses that the fault on the line n is not activated. For example, the error behavior 4 (FPP) shows that the fault is activated at time 1 and it is not activated at time 2 and 3. In k-cycle capture testing, the number of error behaviors for a universal logical fault is -1. In the proposed fault diagnosis method, diagnostic fault simulation for -1 error behaviors of a universal logical fault on each line is performed.In fault diagnosis for universal logical faults, fault simulation with only fail test sequences is performed and suspicious candidate faults are deduced. Because a fault excitation condition of a universal logical fault is unclear, whether defects are activated or not on pass test sequences cannot be judged. Therefore, in this paper, any pass test sequences are not used for the fault diagnosis.In the proposed fault diagnosis method, fault simulation for candidate faults using each fail test sequence is performed and the simulated values at (pseudo) primary outputs are compared with the observed test responses. If the simulated values at (pseudo) primary outputs of a faulty circuit with a fault f are the same as the test responses for all fail test sequences, f is deduced as a suspicious candidate fault. Table 2 is an example of fault diagnosis for lines m and n in 3-cycles capture testing. In Table 2, ft1 and ft2 are fail test sequences, the column “n (m)” shows the simulated values of (pseudo) primary outputs for CUT with a universal logical fault n (m) using ft1 and ft2, and the column “test response” shows the test responses of ft1 Fig. 2 Example of a Pass Test Sequence for a Faulty CircuitFig. 3 Example of Misprediction by Stuck-at Fault Simulation3.3 Universal Logical Fault ModelFig. 4 Universal Logical Fault Model (k＝3)Table 1 Error Behaviors of Universal Logical error behavior 1error behavior 2error behavior 3error behavior 4error behavior 5error behavior 6error behavior 73.4 Fault Diagnosis Using Fault Simulation for a Single Universal Fault Model3.4.1 Fault Simulation for a Single Universal Fault Model─ 13 ─Fault Model (k＝3)time1PPPFFFF■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
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