In this paper, we propose a fault diagnosis method for a single universal logical fault model using multi-cycle capture test sets, and evaluate the effectiveness of the method. In the proposed method, suspicious candidate faults are deduced by erroneous path tracing16) and diagnostic fault simulation.The reminder of this paper is organized as follows. In section 2, we describe multi-cycle capture testing. In section 3, we define a universal logical fault model and explain the proposed fault diagnosis method. In section 4, experimental results for ISCAS’89 and ITC’99 benchmark circuits are shown and section5 concludes the paper.Scan testing for VLSIs has been widely used due to its simplicity, high fault coverage, and strong diagnostic support. In a full-scan design circuit, all functional flip-flops (FFs) are replaced with scan FFs which operate in two modes: shift and capture. The shift mode is used to load a test vector into the scan FFs and to observe the test response. In the capture mode, scan FFs operate as functional FFs and capture the test response of the combinational portion for a test vector into themselves. However, in scan testing, since sequential operations are performed for only 1 or 2 cycles at capture mode, enough function operation cannot be performed. It has been reported that fast functional testing is required to improve test quality12). Multi-cycle capture testing13-15) which performs sequential operations for several cycles at capture mode has been proposed to resolve the problem. This testing detects faults through the process of shifting-in test vectors, operating function for k-cycles (k＞1) at capture mode, and shifting-out test responses. Thus, it is considered that multi-cycle capture testing is similar to functional testing. An example of 4-cycle capture testing is shown in Fig.1. In the 4-cycle capture testing, the initial state is set into FFs by shift-in at time 1, the functional operation is performed by the test sequence from time 1 to time 4, and the final state of FFs is observed by shift-out at time 4. In the 4-cycle capture testing, controllable lines are pseudo primary inputs of time 1 and primary inputs of each time, and observable lines are pseudo primary outputs of time 4 and primary outputs of time 4.We define primary terms for fault diagnosis. When test sequences are applied to CUT, (pseudo) primary outputs are classified as follows based on the test results.(Definition 1: fail (pseudo) primary output / pass (pseudo) primary output)A (pseudo) primary output POj is called a fail (pseudo) primary output if errors are observed at POj in one or more test sequences; otherwise POj is a pass (pseudo) primary output.Test sequences are also classified as follows based on the test results.(Definition 2: fail test sequence / pass test sequence)A test sequence ti is called a fail test sequence if on application of ti one or more (pseudo) primary outputs are observed to have error(s); otherwise ti is a pass test sequence.(Definition 3: explainable faults for test responses)Fault simulation is performed for CUT with all test sequences. As the results, when the simulated values of (pseudo) primary outputs for CUT with a fault on a line n are same as the test responses, a fault on a line n is defined as an explainable fault for test responses.Fault diagnosis methods for specified fault models using fault simulation have been proposed. In these methods, first, the product set of detectable faults for each fail test sequence is generated as an initial suspicious candidate fault set. Next, the union set of detectable faults for each pass test sequence is generated. Finally, the union set is subtracted from the initial suspicious candidate fault set, and a final suspicious candidate fault set is generated.Fig.2 is an example of testing. In Fig.2, when the test sequence, (a, b, c, e)＝(1, 1, 0, 1), is applied to the circuit with the bridging defect between a and b, 0 which is the same as the fault-free value is observed at the primary output j. This test sequence is the pass test sequence.Fig.3 is an example of the final suspicious candidate fault set generation using stuck-at fault simulation with the pass test sequence, (a, b, c, e)＝(1, 1, 0, 1). The current suspicious candidate fault set is supposed to F＝{a/0, b/0, g/0}, where a/0, b/0, and g/0 are stuck-at 0 fault on a, stuck-at 0 fault on b, 3.1 Preliminary Definitions3.2 Problems of Fault Diagnosis Methods for Specified Fault Models─ 12 ─■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■Fig. 1 Example of 4-cycle Capture Testing■■■■■■■■■■■■■■■■■■■■■2. Multi Cycle Capture Testing3. Fault Diagnosis for a Single Universal Logical Fault Model
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