Abstract─ 11 ─ ＊Professor, Department of Mathematical Information Engineering, College of Industrial Technology, Nihon University ＊＊Graduate School of Industrial Technology, Nihon University ＊＊＊Assistant Professor, Department of Liberal Arts and Basic Sciences, College of Industrial Technology, Nihon University＊＊＊＊Associate Professor, School of Information and Communication, Meiji UniversityFault diagnosis methods for specified fault models might deduce wrong faults as suspicious candidate faults (misprediction). The methods might not be able to also deduce suspicious candidate faults (non-prediction). In this paper, we do not classify a logical fault model which changes logical function of a circuit and define a logical fault to a signal line. In multi-cycle capture testing, a universal logical fault model is expressed in whether a fault on a signal line is activated or not at each time frame. A fault diagnosis method for a single universal logical fault model in scan testing is proposed. In the fault diagnosis method, a diagnostic fault simulation for a single universal logical fault model with a multi-cycle capture test set is used. The number of mispredictions, the number of non-predictions, the number of suspicious candidate faults, and fault diagnosis time are evaluated compared with a fault diagnosis method for a single stuck-at fault model. Experimental results for ISCAS’89 and ITC’99 benchmark circuits show the effectiveness of our proposed method.Keywords: Fault Diagnosis, Universal Logical Fault Model, Multi-cycle Capture Testing, Diagnostic Fault SimulationFailure analysis1) is the process to locate physical defects in a faulty circuit. With the shrinking process technologies, failure analysis becomes important to improve the yield. However, failure analysis is a laborious process since analysis equipment such as an electron microscope is used. Therefore, fault diagnosis, the process of deducing suspicious candidate faults, is important to reduce the cost.A number of fault location techniques for specific fault models such as stuck-at faults and bridging faults have been proposed2-6). However, fault diagnosis methods for specified fault models might deduce wrong faults as suspicious candidate faults (misprediction)17). The methods might not be able to also deduce suspicious candidate faults (non-prediction)17). Since it is impossible to predetermine what kind of faults exist in circuits under the test (CUT), it is important to develop a technique capable of diagnosing any logical faults. Some methods to diagnose any logical faults in combinational circuits have been proposed7-11). However, these methods do not consider sequential circuits.In order to improve test quality of scan testing, fast functional testing is important12). Multi-cycle capture testing13-15) is one of the methods for fast functional testing. In multi-cycle capture testing, test sequences with multiple capture cycles are generated, and CUT sequentially operates for two or more cycles for each test sequence. Usually, the number of sequential operations in multi-cycle capture testing is not so large. Therefore, suspicious candidate faults in sequential circuits are effectively deduced by using multi-cycle capture test sets.（Received February 15, 2021）日本大学生産工学部研究報告Ａ2021年 12 月 第 54 巻 第 ２ 号1. IntroductionResearch NoteToshinori HOSOKAWA＊ Hideyuki TAKANO＊＊ Hiroshi YAMAZAKI＊＊＊ and Koji YAMAZAKI＊＊＊＊A Fault Diagnosis Method Using Fault Simulation for a Single Universal Logical Fault Model
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